Corrected rms error and effective number of bits for sine wave ADC tests
نویسندگان
چکیده
A new definition is proposed for the effective number of bits of an ADC. This definition removes the variation in the calculated effective bits when the amplitude and offset of the sinewave test signal is slightly varied. This variation is most pronounced when test signals with amplitudes of a small number of code bin widths are applied to very low noise ADC's. The effectiveness of the proposed definition is compared with that of other proposed definitions over a range of signal amplitudes and noise levels.
منابع مشابه
Determination of Nonlinearity and Effective Resolution of an A / D Converter for Arbitrary
component in video, radar, communications, high-speed data acquisition and measurement systems. ADC decides the overall accuracy of such systems. Many times the input to ADC in an application is different than standard signals such as sine wave or triangular wave. As ADC parameters are dependent on input frequency and other test conditions so parameters determined using standard signals are not...
متن کاملDesign of High Speed Sine Wave Flash Adc for Uwb Applications
Multigigahertz flash ADC is limited by sampling clock timing jitter. Since it is used in high frequency applications it is essential to remove jitter effects which will reduce the efficiency of ADC. This paper describes the effect of clock transition time on the spurious free dynamic range of a CMOS sample and hold circuit. To improve SFDR the effect of finite clock transition time of the signa...
متن کاملIntegral non-linearity error measurement through statistical analysis of a multi-tone test signal
Conventionally, the integral non-linearity of an analogue to digital converter (ADC) is measured using a pure sine wave test signal [1]. The measured amplitude probability distribution function (APDF) of the ADC output is compared with the ideal distribution and the differences used to calculate integral non-linearity error (INL). Accuracy of this method is limited by the practical problem of g...
متن کاملDesign and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA
This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...
متن کاملA 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration
A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a 0.13 μm CMOS process. A digital calibration of DC reference voltage is proposed for the 1 preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to elimin...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- Computer Standards & Interfaces
دوره 26 شماره
صفحات -
تاریخ انتشار 2004